In many areas of modern computer science it has become the practice to exploit at least some form of parallelism through the use of techniques such as multi-thread and/or multi-core processing.
A thread refers to a respective sequence of instructions and a multi-thread processor enables multiple threads to be executed in parallel on a given processor core. For example this parallelism may be achieved by interleaving the instructions of the different threads through the same execution unit or pipeline of the core, or each thread may be run on a respective one of multiple execution units or pipelines of the same core (the execution units being part of the same core in that they share certain other resources or hardware such as memory on the same die). Each thread may also be supported by a respective set of registers, referred to as a context. The context used for a thread may comprise the thread's program counter, a status register, and operand registers for storing operands of the thread. The contexts facilitate the parallel execution of the threads, e.g. by retaining the current program state of each thread while switching between threads in an interleaved implementation.
It is also possible to create a processor comprising multiple cores on the same integrated circuit (IC) die, multiples die in the same chip package, or even an array of interconnected chip packages on the same board. Further, one or more of the multiple cores may be equipped with multi-threading capability so as to execute multiple threads on the respective core.
International patent application publication number WO 2009/007170 discloses a switch-based interconnect architecture by which a thread running on one multi-threaded processor core can communicate with another thread on the same core or a different core. Each core comprises a plurality of channel terminals, also referred to as “channel ends”. Each channel end is a block comprising an input buffer, output buffer and associated registers. The channel ends can be dynamically claimed by threads, and dynamically connected together to form channels between threads over the interconnect. The channel ends can then subsequently be disconnected from one another and released by the threads, to be re-used to form other channels between other combinations of threads. The interconnect comprises a system of switches which route messages to the specific destination channel ends of the respective channels.
Processor cores based on this technology are currently on the market sold under the trade name xCORE, and a corresponding interconnect goes under the name xCONNECT. Each thread sees the threads on the other core or cores according to the same interconnect protocol as it does the threads on the same core. Hence from a higher-level software developer's point of view, each thread may be considered as a respective “logical core” regardless of which physical core it happens to be implemented on.
A core can also connect to other, external components via one or more separate ports. A component accessed via a port is not integrated into the same interconnect system as the inter-thread communications between the threads on the various cores.